Field of the Invention
The invention relates to a refresh control circuit and a refresh control method of a volatile semiconductor memory device such as a dynamic random access memory (DRAM), etc., and a volatile semiconductor memory device.
Description of Related Art
FIG. 1 is a circuit diagram of a structure example of a memory cell MC1 of a conventional DRAM and a refresh control circuit. In FIG. 1, a refresh controller 10 and a latch type sense amplifier 11 are included, bit line BL and/BL are connected to the latch type sense amplifier 11, a general-memorizing the memory cell MC1 includes a metal oxide semiconductor (MOS) transistor Q1 and a capacitor C1. The capacitor C1 is formed by clamping an insulation film by using a pair of electrode films. A latch-type sense amplifier 11 reads a memory voltage Vsn from a drain of the MOS transistor Q1 of the memory cell MC1 through a bit line BL to perform data determination. When charges are accumulated in the capacitor C1, the MOS transistor Q1 is in a reverse bias state, and the capacitor C1 produces a leak current along a substrate direction to result in charge discharge. Therefore, in the DRAM, regarding the memory cell MC1 of each bit, the state of the memory cell MC1 has to be restored periodically, which is referred to as “refresh”. In view of the refresh, to be specific, a selected word line WL and the bit line BL are used to turn on the select MOS transistor Q1, and a specified memory voltage is charged to the capacitor C1 according to data to be memorized. The refresh is, for example, executed in a time interval of 64 ms.
It is assumed that a consuming power consumed in refresh of the DRAM is the same for all of the memory cells, and a consuming current consumed in one refresh operation is fixed, in order to decrease a total consuming current consumed in the refresh operation, a refresh interval can be prolonged to decrease the number of times of the refresh operation in every unit time. However, ideally, the consuming current in self refresh is less, so that the refresh interval is controlled to be as longer as possible within an allowable range of the characteristic (for example, a pause time characteristic) of the memory cell. The pause time characteristic has temperature dependency, and in the memory cell of the DRAM, the higher a temperature is, the shorter a pause time is, and the lower the temperature is, the longer the pause time is.
For example, according to a patent literature 1, in order to decrease the consuming current in a low temperature, a self refresh period of the DRAM is varied according to the temperature dependency of the pause time characteristic. To be specific, a first current generating circuit, a second current generating circuit, a pulse signal generating circuit and a counter circuit construct a timer circuit. The first current generating circuit generates a first current I1 with a positive temperature coefficient, the second current generating circuit generates a second current I2 with a fixed value and substantially without a temperature coefficient, and the pulse signal generating circuit generates a pulse signal with a period corresponding to a sum of the first current I1 and the second current I2 (I1+I2). The counter circuit divides a frequency of the pulse signal generated by the pulse signal generating circuit to output a timer signal.